Add staged RISC-V (riscv64le/riscv32le) Linux payloads#21237
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bcoles wants to merge 1 commit intorapid7:masterfrom
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Add staged RISC-V (riscv64le/riscv32le) Linux payloads#21237bcoles wants to merge 1 commit intorapid7:masterfrom
bcoles wants to merge 1 commit intorapid7:masterfrom
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Add reverse_tcp and bind_tcp stagers and a shell command stage
for both RISC-V 64-bit and 32-bit little-endian Linux targets.
Stagers:
- socket -> connect/bind -> read 4-byte stage length ->
mmap RWX -> read loop -> jump to stage
- Socket fd passed to stage in s1 (x9, callee-saved)
- handle_intermediate_stage sends stage length as 4-byte LE uint
Stages:
- dup3 stdin/stdout/stderr from s1 -> execve("/bin/sh")
- Shell path patchable via SHELL datastore option (16-byte field)
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Add reverse_tcp and bind_tcp stagers and a shell command stage for both RISC-V 64-bit and 32-bit little-endian Linux targets.
Stagers:
Stages:
They were written entirely by Claude. Claude one-shotted them.
Verification
Generate payload:
Set up the stager reverse handler:
Run the generated payload on a RISC-V system. When the stager connects back, the handler automatically sends the 4-byte length + stage. You should get a shell session.